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Micrel, Inc.
MICRF008
proportional to REFOSC frequency. The nominal value
of RSC given in the “Electrical Characteristics ” Table is
VDDBB
20μA
VDDBB
20μA
220k ? for a REFOSC frequency of 3.36MHz. Slicing
level time constant value vary depending on data
pattern, data rate and data duty cycle.
Automatic Gain Control (AGC)
The signal path has automatic gain control (AGC) to
increase the overall receiver dynamic range. An external
capacitor, CAGC, must be connected to the CAGC pin of
the device. Normally the CAGC capacitor is connected
Demod
Signal
(0Vdc)
VSSBB
PHI2B
DC-coupled
Switched
Cap. Filter
TG1
PHI2
VSSBB
Figure 2. CTH Pin
PHI1B
TG2
3.3pF
PHI1
VSSBB
CTH
to ground. If faster start-up times are required when the
receiver is first poweredon, the CAGC capacitor may be
connected to VDD. The ratio of decay-to-attack time
constant is fixed at 10:1 (that is, the attack time constant
is 1/10th of the decay time constant), and the user
cannot change this ratio. Nevertheless, the attack time
constant is set externally by choosing a value for CAGC.
Another function of the AGC control voltage is to raise
the noise floor in order to guarantee a clean signal
between the preamble and the data, sometimes called
dead time. The AGC control voltage can be further
manipulated and amplified to create an RSSI signal,
which is useful for several different applications.
Reference Oscillator
All timing and tuning operations on the MICRF008YM
are derived from the internal Colpitts reference oscillator.
The reference frequency can be implemented in two
ways, by using a resonator device (a ceramic resonator
or crystal), or by driving an external signal, which should
not exceed 0.5VRMS. The reference frequency is
obtained by dividing the RF carrier frequency by 129.
I/O Pin Interface Circuitry
Interface circuitry for the various I/O pins of the
MICRF008 is shown in Figures 2 through 6. Specific
information regarding each of these circuits is discussed
in the following subparagraphs. Not shown are ESD
protection diodes which are applied to all input pins.
CTH Pin
Figure 2 illustrates the CTH pin interface circuit. CTH pin
is driven from a P-Channel MOSFET source-follower
biased with approximately 20 μ A of bias current.
Transmission gates TG1 and TG2 isolate the 3.3pF
capacitor. Internal control signals PHI1/PHI2 are related
in a manner such that the impedance across the
transmission gates looks like a “resistance.” The DC
potential on the CTH pin is approximately 2.2V,
fundamentally determined by the VGS of the two
PChannel MOSFET source-followers shown.
CAGC Pin
Figure 3 illustrates the CAGC pin interface circuit. The
AGC control voltage is developed as an integrated
current into a capacitor CAGC. The attack current is
nominally 15 μ A, while the decay current is a 1/10th
scaling of this, approximately 1.5 μ A. Signal gain of the
RF/IF strip inside the IC diminishes as the voltage on
CAGC decreases. By simply adding a capacitor to
CAGC pin, the attack/decay time constant ratio is fixed
at 1:10.
VDDBB
1.5μA
Compa-
rator
CAGC
15μA
VSSBB
Figure 3. CAGC Pin
DO Pin
The output stage for the Data Comparator (DO pin) is
shown in Figure 4. The output is a 10 μ A push-10 μ A pull,
switched current stage. Such an output stage is capable
of driving CMOS-type loads.
August 2008
7
M9999-080108
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